Hi, I'm Satanu Maity, a Ph.D. scholar seeking Post-Doctoral opportunities.

About Me

I am currently pursuing my Ph.D. at the Indian Institute of Information Technology Guwahati under the supervision of Dr. Manojit Ghose, and I have recently submitted my doctoral thesis. My research focuses on developing approaches to enhance the computational performance of a broad range of applications in hybrid Near-Memory Processing (NMP) architectures, with particular emphasis on computation offloading and memory-system optimization.

I am currently seeking Postdoctoral research opportunities in the areas of computer architecture, memory systems, heterogeneous computing, and high-performance computing.

Prior to my Ph.D., I worked as a Project Assistant under Dr. Dhiman Saha in the Department of Electrical Engineering and Computer Science at Indian Institute of Technology Bhilai from February 2021 to August 2021. Earlier, from August 2019 to February 2021, I served as a faculty member in the Department of Computer Applications at Bengal School of Technology and Management, Hooghly, West Bengal.

Selected Publications

Research papers published in journals and conferences.

SAGE: A Compiler-assisted Reinforcement Learning-based Offloading Approach under Near-memory Processing Paradigm.

Authors: Satanu Maity, Manojit Ghose.

ACM Transactions on Architecture and Code Optimization (TACO), Volume 23, Issue 1, Pages 1-23.

View Paper

A Framework for Near Memory Processing With Computation Offloading and Load Balancing.

Authors: Satanu Maity, Manojit Ghose and Sudeep Pasricha.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 44, Number 9, Pages 3381-3394.

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CoaT: Compiler-Assisted Two-Stage Offloading Approach for Data-Intensive Applications Under NMP Framework.

Authors: Satanu Maity, Mayank Goel and Manojit Ghose.

IEEE Transactions on Emerging Topics in Computing (TETC), Volume 13, Number 3, Pages 753-767.

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Projects

Projects that i've been working on

MCPSim

A hybrid Memory-Centric Processing (MCP) simulator built on top of the Ramulator framework, supporting co-simulation between host processors and MCP processing units across both Near-Memory Processing and Near-LLC Processing architectures. The simulator further enables unified application deployment by leveraging compiler-extracted information, eliminating the need for dynamic profiling tools while improving simulation flexibility and efficiency.

Github Link View Paper

Cache Profiler

An Intel PIN tool–based cache profiler that models a three-level inclusive cache hierarchy.

Github Link